1. Field of the Invention
The present invention relates to processors for use in a multiprocessor system and the like, and more particularly, to processors having a simple construction and an increased capacity of processing when it is used in a multiprocessor system.
2. Description of Related Art
In general, multiprocessor systems require that several processors constituting a multiprocessor system can use a so-called system bus provided in common to all the processors in the multiprocessor system, for example, for access to a large capacity of memory also provided in common in the multiprocessor system. For this purpose, it is necessary to arbitrate requests for the system bus use from the respective processors.
At the earliest stage in the development of multiprocessor system, there had been adopted a method in which when one processor uses the system bus, a HOLD command is given to the other processors to stop their operation. This method is advantageous in that, since no complicated function is needed for arbitrating the use requests of the system bus, the multiprocessor system is simple in the overall construction. However, while one processor uses the system bus, all the processors excluding that one processor have to stop their internal processing. Therefore, the processing capacity of the overall system will be greatly decreased when one processor accesses through the system bus to another external device such as the common memory.
In order to eliminate the above disadvantage, it has been recently proposed to provide a bus arbiter and to perform arbitration by utilizing a wait function of respective processors in a multiprocessor system.
FIG. 1 is a block diagram showing the construction of an exemplary multiprocessor system carrying out the aforementioned arbitrating method. The shown multiprocessor system comprises three processors 1, 2 and 3 and one common memory 4 which are coupled to a system bus 5. Furthermore, to the system bus 5 there is coupled a bus arbiter 6. The three processors 1, 2 and 3 have the same construction, and so, explanation will be made to only one of the processors, i.e., the processor 1. This processor 1 includes a central processing unit (CPU) 11, a local memory 12 and a local input/output (I/O) device 14 which are coupled to each other through an internal bus 15. In addition, an input/output (I/O) interface 16 is provided between the internal bus 15 and the system bus 5. The local I/O device 14 is adapted to be capable of accessing the local memory 12 without intermediary of the CPU 11 but under the control of a controller not shown or the like, so that so called direct memory access (DMA) is possible.
The I/O interface 16 comprises a decoder 20 having an input coupled to the internal bus 15 and an output coupled to a system bus use request (SBUR) line 21. This SBUR line 21 is coupled to the system bus 5 and one input terminal of an AND gate 22, an output of which is coupled to a control terminal of a bus buffer 23 through a bus buffer trigger line 24. The bus buffer 23 is coupled between the system bus 5 and the internal bus 15. The SBUR line 21 is also coupled to one input of another AND gate 25, whose output is coupled to the internal bus 15 through a WAIT line 26. Furthermore, a system bus use acknowledgment (SBUA) line 27 and an access completion line 28 extend from the system bus 5 to respective inputs of a NOR gate 29 which has an output coupled to the other input of the AND gate 25. The SBUA line 27 is also coupled to the other input of the AND gate 24.
With the above construction, when the CPU 11 of the processor 1 attempts to use the system bus 5 for access for example to the common memory 4, the CPU 11 delivers the address signal for the common memory 4, a control signal, and also data in the case of a writing, through the internal bus 15 to the I/O interface 16. The decoder 20 in the I/O interface 16 decodes a portion or all of the address and control signals input thereto and outputs on the SBUR line 21 a system bus use request (SBUR) signal of a logical high level, which is in turn input to the one input of the AND gate 25. At this time, since no signal is input to either of the two inputs of the NOR gate 29, the NOR gate 29 maintains its output coupled to the other input of the AND gate 25 at a logical high level. Therefore, the AND gate 25 enables the WAIT line 26 which is coupled through the internal bus 15 to the CPU 11. Thus, the CPU 11 is rendered to a WAIT condition while retaining the right to use the internal bus 15. On the other hand, since a signal is not supplied to the other input of the AND gate 22, the bus buffer 23 has not yet been triggered.
Furthermore, the SBUR signal on the line 21 is delivered through the system bus 5 to the arbiter 6. This arbiter 6 ceaselessly monitors the status of the system bus 5 and the condition of the system bus use requests from the respective processors, and furnishes a system bus use acknowledgment (SBUA) signal on the SBUA line 27 as soon as the access of the processor 1 to the system bus 5 becomes allowable. This SBUA signal on the line 27 is fed to the NOR gate 29 and the AND gate 22. As a result, the AND gate 22 enables the bus buffer trigger line 24 leading to the bus buffer 23, so that the address, the control signal and the data in the case of writing are outputted through the bus buffer 23 to the system bus 5 and then to the common memory 4.
When the access to the common memory 4 is completed, the common memory 4 outputs an access completion signal on the line 28 coupled through the system bus 5 to the processor 1, where it is inputted to one input of the NOR gate 29. At this time, since the SBUA signal has already been input to the other input of the NOR gate 29, the output of the NOR gate 29 is disabled. As a result, the AND gate 25 is closed, so that the WAIT signal disappears and the processor 11 is released from the WAIT condition.
In the conventional multiprocessor system as mentioned above, each of the processors 1 to 3 is no way unconditionally brought into a HOLD condition at every time one of the processors furnishes a system bus use request. However, as mentioned above, the CPU of each processor is rendered to the WAIT condition while retaining the right to use its internal bus from the time at which the same processor dispatches the system bus use request. Because of this, the following two significant problems have been encountered in the conventional multiprocessor system:
First, in the condition that many system bus used requests are rushed simultaneously or for a short time, a considerable number of processors would entail a long time from the moment of the dispatch of the system bus use request until the moment of the actual receipt of the system bus use acknowledgment. During the period of such a WAIT time, in the processor which has dispatched the system bus use request, even if an internal processing request is issued from the local I/O device or other devices to the local memory or other devices, since the internal bus is occupied or reserved by the CPU in the WAIT condition, the processor cannot carry out the internal processing. This results in decrease of the processing capacity of the individual processors.
Secondly, after the CPU of each processor supplies the internal bus with the address signal, the control signal and also the data signal to be outputted to the system bus, the CPU is put in the WAIT condition. Therefore, when the bus buffer in the I/O interface responds to the system bus use acknowledgment so as to output to the system bus the above signals supplied through the internal bus, it is necessary to newly adjust the output timing of these signals by using, for example, delay circuits or the like. Because of this, the bus buffer in the conventional system has a very complicated construction.